Conventional interfaces of DDR4 SDRAM (double data rate fourth generation synchronous dynamic random-access memory) operate at data rates of up to 3.2 gigabits per second. Channel degradation can cause a data eye at a receiver side of the interface to be closed. Dielectric and resistive losses of printed-circuit-board traces contribute to the channel degradation. The traces present frequency dependent attenuations that cause pulse dispersions and inter-symbol interference (ISI). Impedance discontinuities from connectors and via stubs in the signal path cause reflections that generate more ISI and further reduce a signal-to-noise ratio. As the data rate of a DDR4 SDRAM is increased, the channel loss and the reflections become significant.
It would be desirable to implement a single-ended signal slicer with a wide input voltage range.